secded

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Here are 4 public repositories matching this topic...

spzbrnmrc / ECC-SV_Generator

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Tool to Generate SystemVerilog Code for Single-Error-Correction/Double-Error-Detection Modules

security ecc riscv verilog systemverilog secded

Updated Jul 7, 2025
Python

iDoka / hdl-secded-producer

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MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.

asic fpga ecc matlab octave rtl verilog xilinx altera soc vlsi hamming error-detection error-correction secded hammgen xapp383 xapp645

Updated Dec 27, 2022
MATLAB

StackedArchitect / Fault-Tolerant-RISCV

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A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor

Updated Jun 26, 2025
Verilog

guru-irl / novel-BEC

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Matlab Implementation of "A Novel Approach to Improving Burst Errors Correction Capability of Hamming Code". http://ieeexplore.ieee.org/document/4348260/

matlab error burst correction hamming secded

Updated Sep 21, 2018
MATLAB

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