computerorganization

💯 CSPostgraduate 计算机考研 408 专业课资料及真题资源

CSE GATE - 2020

📟 RISC-V (RV32I) assembly programs from Computer Organization & Architecture (COA) lab sessions — covering arithmetic, branching, memory access, loops, and array handling.

Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory

2025考研二战备考经历 | 考试科目 11408 | 报考专业 081200 | 考研

Computer Organization

Marmara University 3rd year course

Created a virtual machine including CPU, assembler, and RISC from scratch using JAVA

Tic-tac-toe is played on a three-by-three grid by two players, who alternately place the marks X and O in one of the nine spaces in the grid.

A Simpler RISC-V Simulator designed to execute machine readable assembly instructions and perform required operations and update values in real Register Type Simulations. Built using RISC-V assembly coding instructions and python programming language.

Computer Organization (Assembly and Verilog Languages) MIPS Assembly, Syscalls, Processor, Verilog, ALU module, Instructions, Memory module, Register module, FPGA

Contains all projects from my computer science classes at LSU

Computer Systems Organization

Computer Organization & Architecture Project

nand2tetris

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

A Simpler RISC-V Assembler designed to convert Assembly Instructions into Machine Readable Binary Codes. Built using RISC-V assembly coding instructions and python programming language.

This repository is used to save the lecture powerpoint, assignments and labs.