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bitstreams

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This project utilizes a Verilog Register Transfer Level hardware implementation to convert compressed bitstream data to its original uncompressed 320x240 pixel image. This project involves interfacing with various controllers (eg. VGA, UART), developing a state table to establish Finite State Machines to load data, perform matrix multiplication,…

  • Updated Sep 21, 2020
  • Verilog

Real-time bitstream malware detection using an ML + DL model trained on SOTA benchmarks, sourced via Trust-Hub. Includes feature extraction, Trojan detection, family classification, and embedded inference on PYNQ-supported FPGA boards.

  • Updated Aug 28, 2026
  • Tcl

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